1. Field of the Invention
The present invention relates to electronic design automation (EDA) for integrated circuits. In particular, the present invention relates to an EDA tool for estimation of currents or voltages based on a circuit description of a given level of abstraction.
2. Description of the Related Art
Current flow characteristics are important design considerations in an integrated circuit (IC). Thus, the ability to accurately estimate current flow characteristics is very valuable. During the design phase, several current measuring types are typically applied. These measuring types include, for example:
Average Currentxe2x80x94typically used to determine operating temperatures and battery life; average current is typically measured over a relatively long time period, such as over tens, hundreds or thousands of clock cycles.
RMS Currentxe2x80x94typically used for estimating long term reliability effects (e.g., electromigration); RMS current, like average current, is typically measured over a relatively long time period, such as tens, hundreds or thousands of clock cycles.
Peak Sustained Currentxe2x80x94measures the maximum average current sustained over a period of time (e.g., hundreds or thousands of clock cycles).
Instantaneous Currentxe2x80x94typically used to determine the maximum voltage excursions on power supply lines; instantaneous current refers to a current drawn over a short time interval (e.g., a time interval that is equal to or less than the smallest signal transition duration).
Worst Case Instantaneous Currentxe2x80x94measures the maximum instantaneous current that can flow at any given time.
While numerous methods exist for measuring the current flow characteristics of a fabricated integrated circuit, few predictive methods are available to be used during the design phase. The paucity of predictive methods is partly due to the size of the data set required for accurate calculations.
Existing methods for current calculations can be classified according to design abstraction level, calculation method, and measurement type. The abstraction levels at which these calculations are performed are transistor level, logic or gate level, and register-transfer level (RTL). The calculation methods are dynamic and vectorless. Dynamic methods utilize, for example, time- or cycle-based simulators to generate representative activities in the circuit, which can then be used for power or current calculations. In contrast, vectorless methods (also known as static methods) may utilize, for example, probabilistic methods to calculate expected values of power or current. The current measurement types include average current, peak sustained current, and instantaneous current, which are already briefly described above.
Both static and dynamic methods are applicable at the transistor level, and all current measurement types can be estimated at the transistor level. However, not all current measurement types can be estimated in practice using static and dynamic methods. On one hand, due to the computational complexity resulting from the size of state-of-the-art integrated circuits, dynamic methods have become impractical. On the other hand, existing vectorless methods grossly over-estimate, resulting in unrealistic worst case results. For these and other reasons, transistor level methods are not effectively or efficiently used for estimation on an entire integrated circuit.
As in the transistor level, both static and dynamic methods are applicable at the logic or gate level, and all current measurement types can be estimated at the gate level. At the gate level also, not all current measurement types can be estimated in practice using static and dynamic methods. While the circuit at the gate level contains less circuit elements than the corresponding circuit at the transistor level, the computational complexity still renders dynamic methods impractical. Similarly, vectorless methods at the gate level also suffer the same deficiencies as vectorless methods at the transistor level.
At the RTL, as at the transistor level and the gate level, both static and dynamic techniques are available and all current measurement types can be estimated. At the RTL, in practice, accurate dynamic simulations are possible for estimating some current measurement types (e.g., average current), but not for other current measurement types (e.g., instantaneous current). Vectorless methods at the RTL also suffer the same deficiencies as its counterparts at the transistor and the logic gate levels.
In a power grid analysis of an integrated circuit, an estimation of worst-case instantaneous power (or, more specifically, instantaneous current flow) is desirable. In the prior art, however, most power tools can calculate only an average power consumption or an average current flow. An instantaneous current is determined from circuit elements that switch at the instant the current is measured, while average power (hence, average current) is determined from all elements that switch in aggregate over some period of time. Typically, an average current aggregates over a lengthy period of time (e.g., over a few milliseconds to a few seconds). A worst-case instantaneous current for a given simulation or stimulus, however, is determined by taking the maximum current flowing at any point in time over the length of a particular simulation vector set. The calculation of this value is straightforward (i.e., Idd=Max(Itimestepxe2x80x94n) over all timesteps). However, this worst-case instantaneous current is not necessarily the actual worst case because the simulation vector set may not have exercised the worst-case situation.
In integrated circuit design, the term xe2x80x9cworst casexe2x80x9d refers to the worst operating condition for the integrated circuit that can arise. For example, a worst-case peak instantaneous current for a given circuit may be 1 ampere. Often, however, this worst-case condition may not be known until after the integrated circuit is fabricated. Thus, an ability to estimate this peak instantaneous value prior to committing the integrated circuit to silicon is of great importance. However, different estimation methods can yield different values for the estimated worse case. One technique may estimate the worst case current to be 1.2 amperes while another method estimates it to be 3 amperes. Clearly, even though both estimates are xe2x80x9cworst-casexe2x80x9d estimates, there are differences in accuracy and efficacy. It would be valuable to be able to classify the 3-ampere estimate as an xe2x80x9cOverly Conservative Worst Casexe2x80x9d estimate, if the value is so far beyond the actual worst case as to be unrealistic (hence, of little or no value), and to be able to classify the 1.2-ampere estimate as a xe2x80x9cReasonable Worst Casexe2x80x9d estimate, if the estimate is a reasonable approximation to the actual worst case.
The present invention provides an integrated circuit (IC) power analysis tool, which receives an integrated circuit represented at a given level of abstraction, such as the register-transfer level (RTL), the gate level or the transistor level, to accurately calculate the worst-case instantaneous current waveform of an IC using a vectorless technique. The present invention allows a current waveform to be accurately estimated (relative to an actual worst-case current) without requiring an extensive dynamic simulation of the circuit.
In one embodiment, the shape of the current waveform, a peak value of the current waveform, and a maximum value of the derivative of the current waveform with respect to time can be estimated. A method according to the present invention takes advantage of the facts: (a) a clock edge generates significant signal activity, and hence a large number of current-consuming events, and (b) the transitions of clock signals are necessarily highly correlated to worst-case current consumption.
According to one embodiment of the present invention, a device under test (DUT) is pre-conditioned to a state such that when a clock signal transitions, the resulting switching in the combinational logic produce a worst-case current waveform for the device. In that embodiment, a schedule of the state changes resulting from the clock edge is estimated. The schedule represents a sequence of current-consuming eventsxe2x80x94each cell in the device has associated with it a start time, an end time, and a current waveform. The start and end time times represent when the current-consuming event begins and ends, and the estimated current waveform between these times represents the estimated current for the cell during the current-consuming event. The current waveform estimate is based on information from a static timing analysis (STA) and each individual cell""s timing and power models. The STA timing information indicates when nodes in each cell would switch. The power model defines power events during which nodes in the cell would switch, and the current associated with each event.
For instantaneous current calculations, a worst-case peak of the current waveform is determined primarily from the activity in the clock network and the activity in all the storage elements.
The present invention provides a much higher accuracy over methods in the prior art.
A method of the present invention reliably estimates worst-case instantaneous current to correctly validate power grids even in circuits with large peak currents and small noise margins typical of high power consumption, low supply voltage integrated circuits. The worst-case instantaneous current estimate is accomplished without using simulation at the gate level as a source of activity data.
The present invention is better understood upon consideration of the detailed description below and the accompanying drawings.